Integrated circuits may be formed using photolithography processes with illuminations sources having wavelengths more than twice a desired pitch of metal interconnect lines in the integrated circuits. Attaining desired tradeoffs between fabrication costs and fabrication yield may be difficult. For example, technology nodes at and beyond the 28 nanometer node using 193 nanometer illumination sources may require more than one pattern step to obtain desired first metal interconnect layouts. Providing design rules, optical proximity correction (OPC) rules and optimizing illumination source models to form short lines, terminated lines and crossovers between adjacent parallel route tracks with desired lateral dimensions may be problematic.